Can I program a platform independent PLL in VHDL?
$begingroup$
Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom vendor specific IP of the FPGA, that must be configured and placed in the design.
Is there a way around this? Can I program/define my own PLL in VHDL, that is preferably synthesized using the internal hard coded PLL blocks of the FPGA and works for Altera and Xilinx without having to manually insert the PLL to a project via MegaWizard & Cons?
fpga vhdl pll
asked 6 hours ago
SDwarfsSDwarfs
44028
$endgroup$
add a comment |
$begingroup$
Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom vendor specific IP of the FPGA, that must be configured and placed in the design.
Is there a way around this? Can I program/define my own PLL in VHDL, that is preferably synthesized using the internal hard coded PLL blocks of the FPGA and works for Altera and Xilinx without having to manually insert the PLL to a project via MegaWizard & Cons?
fpga vhdl pll
asked 6 hours ago
SDwarfsSDwarfs
44028
$endgroup$
2
$begingroup$
clock generation and distribution is, if you like, a 'level below' the standard logic fabric. There is so much riding on the cross chip skew, and power dissipation associated with huge nets, that it's optimised to the Nth for any particular device, family, vendor etc etc. You could make a generic multiplier, but you'd have to route it through the dedicated clock buffers into the clocking infrastructure, and then it wouldn't perform anything like the dedicated resources. With clocking, you just have to suck up what you're given on a part by part basis.
$endgroup$
– Neil_UK
6 hours ago
1
$begingroup$
Besides the input @Neil_UK gave, why is the the IP a problem for you? You could just generate the IP than look into the generated files and if you are lucky the part of the code you are looking for isn't enrypted. Also, you can just write a code wrapper, like with constants and generate statements f.E. which instantiates the component depending on your hardware.
$endgroup$
– Eggi
5 hours ago
$begingroup$
Yeah, that would be a possibility. However, is there any way to avoid those IP-Managers? Something like "#ifdef XILINX" constructs for actually using the one or the other generated IP dependent? --- Main issue is: I want to avoid using any GUI wizzards, instead have VHDL and other source files that might be generated by some external tool.
$endgroup$
– SDwarfs
5 hours ago
$begingroup$
If you want ifdef's you should switch to Verilog. And I agree the Xilinx GUI was great until some @~$£%$ [censored] decided to go back to schematics.
$endgroup$
– Oldfart
5 hours ago
add a comment |
$begingroup$
Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom vendor specific IP of the FPGA, that must be configured and placed in the design.
Is there a way around this? Can I program/define my own PLL in VHDL, that is preferably synthesized using the internal hard coded PLL blocks of the FPGA and works for Altera and Xilinx without having to manually insert the PLL to a project via MegaWizard & Cons?
fpga vhdl pll
asked 6 hours ago
SDwarfsSDwarfs
44028
$endgroup$
Most FPGA developement boards have a 50 MHz clock source onboard. However, the FPGAs are typically able to work faster than this. For multiplying the clock speed it seems to be needed to use a custom vendor specific IP of the FPGA, that must be configured and placed in the design.
Is there a way around this? Can I program/define my own PLL in VHDL, that is preferably synthesized using the internal hard coded PLL blocks of the FPGA and works for Altera and Xilinx without having to manually insert the PLL to a project via MegaWizard & Cons?
fpga vhdl pll
fpga vhdl pll
asked 6 hours ago
SDwarfsSDwarfs
44028
asked 6 hours ago
SDwarfsSDwarfs
44028
asked 6 hours ago
SDwarfsSDwarfs
44028
asked 6 hours ago
SDwarfsSDwarfs
44028
asked 6 hours ago
SDwarfsSDwarfs
44028
44028
2
$begingroup$
clock generation and distribution is, if you like, a 'level below' the standard logic fabric. There is so much riding on the cross chip skew, and power dissipation associated with huge nets, that it's optimised to the Nth for any particular device, family, vendor etc etc. You could make a generic multiplier, but you'd have to route it through the dedicated clock buffers into the clocking infrastructure, and then it wouldn't perform anything like the dedicated resources. With clocking, you just have to suck up what you're given on a part by part basis.
$endgroup$
– Neil_UK
6 hours ago
1
$begingroup$
Besides the input @Neil_UK gave, why is the the IP a problem for you? You could just generate the IP than look into the generated files and if you are lucky the part of the code you are looking for isn't enrypted. Also, you can just write a code wrapper, like with constants and generate statements f.E. which instantiates the component depending on your hardware.
$endgroup$
– Eggi
5 hours ago
$begingroup$
Yeah, that would be a possibility. However, is there any way to avoid those IP-Managers? Something like "#ifdef XILINX" constructs for actually using the one or the other generated IP dependent? --- Main issue is: I want to avoid using any GUI wizzards, instead have VHDL and other source files that might be generated by some external tool.
$endgroup$
– SDwarfs
5 hours ago
$begingroup$
If you want ifdef's you should switch to Verilog. And I agree the Xilinx GUI was great until some @~$£%$ [censored] decided to go back to schematics.
$endgroup$
– Oldfart
5 hours ago
add a comment |
2
$begingroup$
clock generation and distribution is, if you like, a 'level below' the standard logic fabric. There is so much riding on the cross chip skew, and power dissipation associated with huge nets, that it's optimised to the Nth for any particular device, family, vendor etc etc. You could make a generic multiplier, but you'd have to route it through the dedicated clock buffers into the clocking infrastructure, and then it wouldn't perform anything like the dedicated resources. With clocking, you just have to suck up what you're given on a part by part basis.
$endgroup$
– Neil_UK
6 hours ago
1
$begingroup$
Besides the input @Neil_UK gave, why is the the IP a problem for you? You could just generate the IP than look into the generated files and if you are lucky the part of the code you are looking for isn't enrypted. Also, you can just write a code wrapper, like with constants and generate statements f.E. which instantiates the component depending on your hardware.
$endgroup$
– Eggi
5 hours ago
$begingroup$
Yeah, that would be a possibility. However, is there any way to avoid those IP-Managers? Something like "#ifdef XILINX" constructs for actually using the one or the other generated IP dependent? --- Main issue is: I want to avoid using any GUI wizzards, instead have VHDL and other source files that might be generated by some external tool.
$endgroup$
– SDwarfs
5 hours ago
$begingroup$
If you want ifdef's you should switch to Verilog. And I agree the Xilinx GUI was great until some @~$£%$ [censored] decided to go back to schematics.
$endgroup$
– Oldfart
5 hours ago
2
2
$begingroup$
clock generation and distribution is, if you like, a 'level below' the standard logic fabric. There is so much riding on the cross chip skew, and power dissipation associated with huge nets, that it's optimised to the Nth for any particular device, family, vendor etc etc. You could make a generic multiplier, but you'd have to route it through the dedicated clock buffers into the clocking infrastructure, and then it wouldn't perform anything like the dedicated resources. With clocking, you just have to suck up what you're given on a part by part basis.
$endgroup$
– Neil_UK
6 hours ago
$begingroup$
clock generation and distribution is, if you like, a 'level below' the standard logic fabric. There is so much riding on the cross chip skew, and power dissipation associated with huge nets, that it's optimised to the Nth for any particular device, family, vendor etc etc. You could make a generic multiplier, but you'd have to route it through the dedicated clock buffers into the clocking infrastructure, and then it wouldn't perform anything like the dedicated resources. With clocking, you just have to suck up what you're given on a part by part basis.
$endgroup$
– Neil_UK
6 hours ago
1
1
$begingroup$
Besides the input @Neil_UK gave, why is the the IP a problem for you? You could just generate the IP than look into the generated files and if you are lucky the part of the code you are looking for isn't enrypted. Also, you can just write a code wrapper, like with constants and generate statements f.E. which instantiates the component depending on your hardware.
$endgroup$
– Eggi
5 hours ago
$begingroup$
Besides the input @Neil_UK gave, why is the the IP a problem for you? You could just generate the IP than look into the generated files and if you are lucky the part of the code you are looking for isn't enrypted. Also, you can just write a code wrapper, like with constants and generate statements f.E. which instantiates the component depending on your hardware.
$endgroup$
– Eggi
5 hours ago
$begingroup$
Yeah, that would be a possibility. However, is there any way to avoid those IP-Managers? Something like "#ifdef XILINX" constructs for actually using the one or the other generated IP dependent? --- Main issue is: I want to avoid using any GUI wizzards, instead have VHDL and other source files that might be generated by some external tool.
$endgroup$
– SDwarfs
5 hours ago
$begingroup$
Yeah, that would be a possibility. However, is there any way to avoid those IP-Managers? Something like "#ifdef XILINX" constructs for actually using the one or the other generated IP dependent? --- Main issue is: I want to avoid using any GUI wizzards, instead have VHDL and other source files that might be generated by some external tool.
$endgroup$
– SDwarfs
5 hours ago
$begingroup$
If you want ifdef's you should switch to Verilog. And I agree the Xilinx GUI was great until some @~$£%$ [censored] decided to go back to schematics.
$endgroup$
– Oldfart
5 hours ago
$begingroup$
If you want ifdef's you should switch to Verilog. And I agree the Xilinx GUI was great until some @~$£%$ [censored] decided to go back to schematics.
$endgroup$
– Oldfart
5 hours ago
add a comment |
1 Answer
1
active
oldest
votes
$begingroup$
You can do this by including vendor specific primitives in your code.
Both Xilinx and Altera have PLL primitives that can be instantiated in the source code with no gui.
Xilinx:
PLL2_ADV and PLL_BASE (from page 351 onward)
Altera:
altpll User guide
While the Altera AltPLL IP does have a gui (and they highly recommend you use it, due to the wide range of PLL configuration parameters they have available), you don't actually have to use the GUI. Or, you can use the GUI once and then just keep the vhdl file it generates. I tested this by removing the IP gui file (.qip) from the project and added the source only, and it synthesized fine.
In both cases, you'll need to include the libraries at the top of your code.
-- Altera
LIBRARY altera_mf;
USE altera_mf.all;
-- Xilinx
LIBRARY UNISIM;
USE UNISIM.vcomponents.all;
The biggest issue is differentiating between vendors. The --pragma directive doesn't have a way to distinguish between vendors, so you'll need to use generate statements to do so. See this answer for more info about that: what is #define equivalent in VHDL
answered 5 hours ago
stanristanri
4,46411847
$endgroup$
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
1
$begingroup$
One globalgenericdefinition of "IS_XILINX" or "IS_ALTERA" and aif-generateat the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.
$endgroup$
– SDwarfs
3 hours ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
add a comment |
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1 Answer
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$begingroup$
You can do this by including vendor specific primitives in your code.
Both Xilinx and Altera have PLL primitives that can be instantiated in the source code with no gui.
Xilinx:
PLL2_ADV and PLL_BASE (from page 351 onward)
Altera:
altpll User guide
While the Altera AltPLL IP does have a gui (and they highly recommend you use it, due to the wide range of PLL configuration parameters they have available), you don't actually have to use the GUI. Or, you can use the GUI once and then just keep the vhdl file it generates. I tested this by removing the IP gui file (.qip) from the project and added the source only, and it synthesized fine.
In both cases, you'll need to include the libraries at the top of your code.
-- Altera
LIBRARY altera_mf;
USE altera_mf.all;
-- Xilinx
LIBRARY UNISIM;
USE UNISIM.vcomponents.all;
The biggest issue is differentiating between vendors. The --pragma directive doesn't have a way to distinguish between vendors, so you'll need to use generate statements to do so. See this answer for more info about that: what is #define equivalent in VHDL
answered 5 hours ago
stanristanri
4,46411847
$endgroup$
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
1
$begingroup$
One globalgenericdefinition of "IS_XILINX" or "IS_ALTERA" and aif-generateat the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.
$endgroup$
– SDwarfs
3 hours ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
add a comment |
$begingroup$
You can do this by including vendor specific primitives in your code.
Both Xilinx and Altera have PLL primitives that can be instantiated in the source code with no gui.
Xilinx:
PLL2_ADV and PLL_BASE (from page 351 onward)
Altera:
altpll User guide
While the Altera AltPLL IP does have a gui (and they highly recommend you use it, due to the wide range of PLL configuration parameters they have available), you don't actually have to use the GUI. Or, you can use the GUI once and then just keep the vhdl file it generates. I tested this by removing the IP gui file (.qip) from the project and added the source only, and it synthesized fine.
In both cases, you'll need to include the libraries at the top of your code.
-- Altera
LIBRARY altera_mf;
USE altera_mf.all;
-- Xilinx
LIBRARY UNISIM;
USE UNISIM.vcomponents.all;
The biggest issue is differentiating between vendors. The --pragma directive doesn't have a way to distinguish between vendors, so you'll need to use generate statements to do so. See this answer for more info about that: what is #define equivalent in VHDL
answered 5 hours ago
stanristanri
4,46411847
$endgroup$
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
1
$begingroup$
One globalgenericdefinition of "IS_XILINX" or "IS_ALTERA" and aif-generateat the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.
$endgroup$
– SDwarfs
3 hours ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
add a comment |
$begingroup$
You can do this by including vendor specific primitives in your code.
Both Xilinx and Altera have PLL primitives that can be instantiated in the source code with no gui.
Xilinx:
PLL2_ADV and PLL_BASE (from page 351 onward)
Altera:
altpll User guide
While the Altera AltPLL IP does have a gui (and they highly recommend you use it, due to the wide range of PLL configuration parameters they have available), you don't actually have to use the GUI. Or, you can use the GUI once and then just keep the vhdl file it generates. I tested this by removing the IP gui file (.qip) from the project and added the source only, and it synthesized fine.
In both cases, you'll need to include the libraries at the top of your code.
-- Altera
LIBRARY altera_mf;
USE altera_mf.all;
-- Xilinx
LIBRARY UNISIM;
USE UNISIM.vcomponents.all;
The biggest issue is differentiating between vendors. The --pragma directive doesn't have a way to distinguish between vendors, so you'll need to use generate statements to do so. See this answer for more info about that: what is #define equivalent in VHDL
answered 5 hours ago
stanristanri
4,46411847
$endgroup$
You can do this by including vendor specific primitives in your code.
Both Xilinx and Altera have PLL primitives that can be instantiated in the source code with no gui.
Xilinx:
PLL2_ADV and PLL_BASE (from page 351 onward)
Altera:
altpll User guide
While the Altera AltPLL IP does have a gui (and they highly recommend you use it, due to the wide range of PLL configuration parameters they have available), you don't actually have to use the GUI. Or, you can use the GUI once and then just keep the vhdl file it generates. I tested this by removing the IP gui file (.qip) from the project and added the source only, and it synthesized fine.
In both cases, you'll need to include the libraries at the top of your code.
-- Altera
LIBRARY altera_mf;
USE altera_mf.all;
-- Xilinx
LIBRARY UNISIM;
USE UNISIM.vcomponents.all;
The biggest issue is differentiating between vendors. The --pragma directive doesn't have a way to distinguish between vendors, so you'll need to use generate statements to do so. See this answer for more info about that: what is #define equivalent in VHDL
answered 5 hours ago
stanristanri
4,46411847
edited 5 hours ago
answered 5 hours ago
stanristanri
4,46411847
answered 5 hours ago
stanristanri
4,46411847
answered 5 hours ago
stanristanri
4,46411847
4,46411847
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
1
$begingroup$
One globalgenericdefinition of "IS_XILINX" or "IS_ALTERA" and aif-generateat the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.
$endgroup$
– SDwarfs
3 hours ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
add a comment |
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
1
$begingroup$
One globalgenericdefinition of "IS_XILINX" or "IS_ALTERA" and aif-generateat the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.
$endgroup$
– SDwarfs
3 hours ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
$begingroup$
Thanks! This should work for me. Also thanks for the pointers to the #define-equivalents.
$endgroup$
– SDwarfs
3 hours ago
1
1
$begingroup$
One global
generic definition of "IS_XILINX" or "IS_ALTERA" and a if-generate at the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.$endgroup$
– SDwarfs
3 hours ago
$begingroup$
One global
generic definition of "IS_XILINX" or "IS_ALTERA" and a if-generate at the target system specific locations (as suggested by the linked Q&A) should do the trick. A global quick to find configuration point is acceptable in my setup.$endgroup$
– SDwarfs
3 hours ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
$begingroup$
@SDwarfs Just to be clear, the answer to the question in the title you wrote is no. Different "platforms", even those from the same vendor, may have different ways of specifying and configuring their PLLs. The approach suggested here works as long as you provide options for all "platforms".
$endgroup$
– Elliot Alderson
1 hour ago
add a comment |
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2
$begingroup$
clock generation and distribution is, if you like, a 'level below' the standard logic fabric. There is so much riding on the cross chip skew, and power dissipation associated with huge nets, that it's optimised to the Nth for any particular device, family, vendor etc etc. You could make a generic multiplier, but you'd have to route it through the dedicated clock buffers into the clocking infrastructure, and then it wouldn't perform anything like the dedicated resources. With clocking, you just have to suck up what you're given on a part by part basis.
$endgroup$
– Neil_UK
6 hours ago
1
$begingroup$
Besides the input @Neil_UK gave, why is the the IP a problem for you? You could just generate the IP than look into the generated files and if you are lucky the part of the code you are looking for isn't enrypted. Also, you can just write a code wrapper, like with constants and generate statements f.E. which instantiates the component depending on your hardware.
$endgroup$
– Eggi
5 hours ago
$begingroup$
Yeah, that would be a possibility. However, is there any way to avoid those IP-Managers? Something like "#ifdef XILINX" constructs for actually using the one or the other generated IP dependent? --- Main issue is: I want to avoid using any GUI wizzards, instead have VHDL and other source files that might be generated by some external tool.
$endgroup$
– SDwarfs
5 hours ago
$begingroup$
If you want ifdef's you should switch to Verilog. And I agree the Xilinx GUI was great until some @~$£%$ [censored] decided to go back to schematics.
$endgroup$
– Oldfart
5 hours ago